1951 IAS Machine Architecture
This section is made to grasp a basic understand of how a computer architecture works, and it's not meant to be studied thoroughly.
The IAS Machine had a 1000 word memory, with a 40b word (40000b = 5000B ~ 5kB).
Word
Words are CA2 integers
| 0 | 000000000000000000000000000000000000000 |
|---|---|
| \(\pm 2^{39} \cdot bit\) | \(value\) |
Instruction words contain two instructions
| 00000000 | 000000000000 | 00000000 | 000000000000 |
|---|---|---|---|
| \(0..7\) | \(8..19\) | \(20..27\) | \(28..39\) |
| opcode | address | opcode | address |
CPU
| Name | Description | |
|---|---|---|
| MBR | Memory Buffer Register | receives & sends data to memory and I/O |
| MAR | Memory Address Register | current memory address |
| PC | Program Counter | address of the instruction to execute |
| IR | Instruction Register | contains instruction to execute |
| IBR | Instruction Buffer Register | contains the second instruction |
| AC | Accumulator | for partial calculation results |
| MQ | Multiplier Quotient | for partial calculation results |
Instructions
This isn't the full ISA of the IAS Machine, check it out here.
Transfer Instructions
| Description | |
|---|---|
| LOAD | AC \(\leftarrow\) AC operation Memory[Address] |
| LOAD | AC \(\leftarrow\) operation Memory[Address] |
| LDMQ | MQ \(\leftarrow\) Memory[Address] |
| ST | Memory[Address] \(\leftarrow\) AC |
| AMODL | Memory[Address][0..11] \(\leftarrow\) AC[0..11] (low) |
| AMODH | Memory[Address][20..31] \(\leftarrow\) AC[0..11] (high) |
Jumps
Like in modern assembly, jumps can be unconditional, conditional; for the IAS machine you had to specify either a low or high address.
| Description | |
|---|---|
| UBL | PC \(\leftarrow\) [Address] |
| UBH | PC \(\leftarrow\) [Address] + 1 |
| CBL | if AC \(\ge\) 0 { PC \(\leftarrow\) [Address] } |
| CBH | if AC \(\ge\) 0 { PC \(\leftarrow\) [Address] + 1 } |
Operations
| Description | |
|---|---|
| MUL | AC, MQ \(\leftarrow\) AC \(\cdot\) Memory[Address] |
| DIV | AC \(\leftarrow\) AC / Memory[Address] |
| DIV | MQ \(\leftarrow\) AC % Memory[Address] |
| LSHIFT | AC, MQ \(\leftarrow\) AC, MQ << X |
| RSHIFT | AC, MQ \(\leftarrow\) AC, MQ >> X |
| MOVE | AC \(\leftarrow\) AC operation MQ |
| IO | Transfer from and to I/O devices |
Example Program
LOAD 101
ADD 102
ST 103
How does it work?
- Fetch
- MAR \(\leftarrow\) PC
- IR, IBR \(\leftarrow\) MBR \(\leftarrow\) Memory[MAR]
- Decode
- MAR \(\leftarrow\) IR[8..19] ; address
- CU \(\leftarrow\) IR[0..8] ; opcode
- Exec
- AC \(\leftarrow\) MBR \(\leftarrow\) Memory[101]
- Decode
- MAR \(\leftarrow\) IBR[8..19] ; address
- CU \(\leftarrow\) IBR[0..8] ; opcode
- Exec
- AC \(\leftarrow\) AC + MBR \(\leftarrow\) Memory[102]
- PC
- PC \(\leftarrow\) PC + 1
- Fetch
- MAR \(\leftarrow\) PC
- IR, IBR \(\leftarrow\) MBR \(\leftarrow\) Memory[MAR]
- Decode
- MAR \(\leftarrow\) IR[8..19] ; address
- CU \(\leftarrow\) IR[0..8] ; opcode
- Exec
- Memory[103] \(\leftarrow\) MBR \(\leftarrow\) AC